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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ID_PFR0, Processor Feature Register 0</h1><p>The ID_PFR0 characteristics are:</p><h2>Purpose</h2>
        <p>Gives top-level information about the instruction sets and other features supported by the PE in AArch32 state.</p>

      
        <p>Must be interpreted with <a href="AArch32-id_pfr1.html">ID_PFR1</a>.</p>

      
        <p>For general information about the interpretation of the ID registers, see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>AArch32 System register ID_PFR0 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-id_pfr0_el1.html">ID_PFR0_EL1[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_PFR0 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>ID_PFR0 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">RAS</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">DIT</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">AMU</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">CSV2</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">State3</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">State2</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">State1</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">State0</a></td></tr></tbody></table><h4 id="fieldset_0-31_28">RAS, bits [31:28]</h4><div class="field">
      <p>RAS Extension version. Defined values are:</p>
    <table class="valuetable"><tr><th>RAS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>No RAS Extension.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>RAS Extension implemented.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td><p><span class="xref">FEAT_RASv1p1</span> implemented. As <span class="binarynumber">0b0001</span>, and adds support for additional ERXMISC&lt;m&gt; System registers.</p>
<p>Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to <a href="ext-errnstatus.html">ERR&lt;n&gt;STATUS</a> and support for the optional RAS Timestamp Extension.</p></td></tr><tr><td class="bitfield">0b0011</td><td>
          <p><span class="xref">FEAT_RASv2</span> implemented. As <span class="binarynumber">0b0010</span>, and requires that error records accessed through System registers conform to RAS System Architecture v2.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_RAS</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p><span class="xref">FEAT_RASv1p1</span> implements the functionality identified by the value <span class="binarynumber">0b0010</span>.</p>
<p><span class="xref">FEAT_RASv2</span> implements the functionality identified by the value <span class="binarynumber">0b0011</span>.</p>
<p>In Armv8.0 and Armv8.1, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.2, the value <span class="binarynumber">0b0000</span> is not permitted.</p>
<p>From Armv8.4, if <span class="xref">FEAT_DoubleFault</span> is implemented or <a href="AArch32-erridr.html">ERRIDR</a>.NUM is nonzero, the value <span class="binarynumber">0b0001</span> is not permitted.</p>
<div class="note"><span class="note-header">Note</span><p>When the value of this field is <span class="binarynumber">0b0001</span>, <a href="AArch32-id_pfr2.html">ID_PFR2</a>.RAS_frac indicates whether <span class="xref">FEAT_RASv1p1</span> is implemented.</p></div></div><h4 id="fieldset_0-27_24">DIT, bits [27:24]</h4><div class="field">
      <p>Data Independent Timing. Defined values are:</p>
    <table class="valuetable"><tr><th>DIT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>AArch32 does not guarantee constant execution time of any instructions.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>AArch32 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_DIT</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.4, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-23_20">AMU, bits [23:20]</h4><div class="field">
      <p>Indicates support for Activity Monitors Extension. Defined values are:</p>
    <table class="valuetable"><tr><th>AMU</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Activity Monitors Extension is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p><span class="xref">FEAT_AMUv1</span> is implemented.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p><span class="xref">FEAT_AMUv1p1</span> is implemented. As <span class="binarynumber">0b0001</span> and adds support for virtualization of the activity monitor event counters.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_AMUv1</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p><span class="xref">FEAT_AMUv1p1</span> implements the functionality identified by the value <span class="binarynumber">0b0010</span>.</p>
<p>In Armv8.0, the only permitted value is <span class="binarynumber">0b0000</span>.</p>
<p>In Armv8.4, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.6, the permitted values are <span class="binarynumber">0b0000</span>, <span class="binarynumber">0b0001</span>, and <span class="binarynumber">0b0010</span>.</p></div><h4 id="fieldset_0-19_16">CSV2, bits [19:16]</h4><div class="field">
      <p>Speculative use of out of context branch targets. Defined values are:</p>
    <table class="valuetable"><tr><th>CSV2</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>The implementation does not disclose whether <span class="xref">FEAT_CSV2</span> is implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p><span class="xref">FEAT_CSV2</span> is implemented, but <span class="xref">FEAT_CSV2_1p1</span> is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p><span class="xref">FEAT_CSV2_1p1</span> is implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_CSV2</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p><span class="xref">FEAT_CSV2_1p1</span> implements the functionality identified by the value <span class="binarynumber">0b0010</span>.</p>
<p>From Armv8.5, the permitted values are <span class="binarynumber">0b0001</span> and <span class="binarynumber">0b0010</span>.</p></div><h4 id="fieldset_0-15_12">State3, bits [15:12]</h4><div class="field">
      <p>T32EE instruction set support. Defined values are:</p>
    <table class="valuetable"><tr><th>State3</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>T32EE instruction set implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-11_8">State2, bits [11:8]</h4><div class="field">
      <p>Jazelle extension support. Defined values are:</p>
    <table class="valuetable"><tr><th>State2</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Jazelle extension implemented, without clearing of <a href="AArch32-joscr.html">JOSCR</a>.CV on exception entry.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>Jazelle extension implemented, with clearing of <a href="AArch32-joscr.html">JOSCR</a>.CV on exception entry.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-7_4">State1, bits [7:4]</h4><div class="field">
      <p>T32 instruction set support. Defined values are:</p>
    <table class="valuetable"><tr><th>State1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>T32 instruction set not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td><p>T32 encodings before the introduction of Thumb-2 technology implemented:</p>
<ul>
<li>
<p>All instructions are 16-bit.</p>

</li><li>
<p>A BL or BLX is a pair of 16-bit instructions.</p>

</li><li>
<p>32-bit instructions other than BL and BLX cannot be encoded.</p>

</li></ul></td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>T32 encodings after the introduction of Thumb-2 technology implemented, for all 16-bit and 32-bit T32 basic instructions.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0011</span>.</p></div><h4 id="fieldset_0-3_0">State0, bits [3:0]</h4><div class="field">
      <p>A32 instruction set support. Defined values are:</p>
    <table class="valuetable"><tr><th>State0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>A32 instruction set not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>A32 instruction set implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><div class="access_mechanisms"><h2>Accessing ID_PFR0</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0000</td><td>0b0001</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T0 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T0 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TID3 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TID3 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        R[t] = ID_PFR0;
elsif PSTATE.EL == EL2 then
    R[t] = ID_PFR0;
elsif PSTATE.EL == EL3 then
    R[t] = ID_PFR0;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:05; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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